1. Field of the Invention
This invention relates generally to memory cells, array structures for memory cells, and methods for writing and reading the memory cells. More particularly, this invention relates to magnetic random access memory (MRAM) cells, array structures for MRAM cells, and methods for writing and reading MRAM cells. Even more particularly, this invention relates to MRAM array cells employed as reference devices for determining a data state retained within an MRAM data cell.
2. Description of Related Art
As shown in FIGS. 1a and 1b, a memory array is generally formed of groups of MTJ cells 10 in columns and rows. Each MTJ cell 10 has an MTJ device 15 for retaining digital data as an orientation of the magnetic fields within the MTJ device 15. Each MTJ device 15 is formed of two layers of magnetic material 16 and 18 isolated from each other by a tunnel barrier 17. The free magnetic layer 18 is adjoined to the bit line 25. The bit line 25 conducts the cell current Icell 35 such that the magnetic field developed by the cell current Ic 35 in the bit line 25 and the row write cell current IR 40 in the row write line conductor 30 determine the magnetic orientation of the free magnetic layer 18 and thus determine the state of digital data within the MTJ cell 15. The write line 30 is close proximity to the MTJ cell 15. The write line 30 conducts a row write cell current IR 40 in one direction. The magnetic orientation of the fixed magnetic layer 16 is determined during manufacturing of the MTJ device 15.
The fixed magnetic layer 16 is adjoined to a conductor 45 that is connected to the drain of an isolation transistor MISO 20. The source of the isolation transistor MISO 20 is connected to the ground reference point. The gate of the isolation transistor MISO 20 is connected to a read word line RWL
In the write operation of the MTJ cell 10, the direction of conduction cell current Icell 35 determines the magnetic orientation of the free magnetic layer 18 and thus the digital data state retained by the MTJ cell 10. During the write process, the read word line RWL 50 deactivates the isolation transistor MISO 20 to prevent current conduction.
The read operation is illustrated in FIG. 1b. The read word line RWL 50 is set to a state to activate or turn on the isolation transistor MISO 20. The cell current Icell 55 is passed through the bit line 25, through the MTJ device 15, and the isolation transistor MISO 20 to the ground reference point. The magnetic orientation of the free magnetic layer 18 as compared to the magnetic orientation of the fixed magnetic layer 16 determine the resistance of the MTJ device 15. FIG. 2 shows the schematic diagram of the MRAM cell 10 with the MTJ device 15 and the isolation transistor MISO 20 serially connected. The read word line RWL 50 controls the activation and deactivation of the isolation transistor MISO 20. The bit line 25 is relative to the free magnetic layer 18 as described above for writing the free magnetic layer 18 and for reading the MTJ cell 10.
Referring now to FIG. 3 for a more detailed description of the read operation of the prior art. A group of MRAM cells 10 are organized in rows and columns to for an MRAM array 5. The bit lines 25 are connected such that they adjoin the free magnetic layers of each MTJ device 15 of each MRAM cell 10 of a column. The write line WL 30 and the read word line RWL 50 are connected for each row of the MRAM cells 10. The write line WL 30 being adjoined to the MTJ device 15 of each of the rows of MRAM cells 10 for writing selected MTJ devices 15 of each of the rows of the MRAM cells 10. The read word line RWL 50 connected to control the activation and deactivation of the isolation transistor MISO 20 of each row of the MRAM cells 10.
During a read operation, the cell current Ic 55 passes through the selected MRAM cell 10. The cell current Icell 55 develops a across the MTJ device 15 which is a first input to the sense amplifier 60. A voltage that is developed at the second input of the sense amplifier 60 is a reference voltage VREF for determining the state of the digital data retained by the MRAM cell 10. The reference voltage VREF is developed across the MRAM reference cell 65. The data voltage VDAT is compared with the reference voltage VREF to determine the digital data retained by the MRAM cell 10.
The MRAM reference cell 65 is formed of the series/parallel combination of MTJ devices 67a and 67b that are magnetized to have a minimum resistance and the MTJ devices 69a and 69b. This series/parallel combination of the MTJ devices 67a, 67b, 69a, and 69b is equivalent to the mid-point resistance of the maximum and minimum resistances of the MTJ devices 67a, 67b, 69a, and 69b. The reference bit line 70 conducts a reference current IREF 75 through the MRAM reference cell 65 to develop the reference voltage VREF at the second input of the sense amplifier 60.
“A 16 Mb MRAM Featuring Bootstrapped Write Drivers”, DeBrosse, et al., Digest of Technical Papers, 2004 Symposium on VLSI Circuits, June 2004 pp.: 454-457 describes a cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. The 16 Mb MRAM uses three-Cu-level CMOS with a three-level MRAM process adder and features a X16 asynchronous SRAM-like interface.
U.S. Pat. No. 6,816,403 (Brennan, et al.) describes a capacitively coupled sensing apparatus for cross point MRAM devices. The apparatus establishes an offset voltage of a sense amplifier. The sense amplifier is selectively coupled to a selected bit line within the MRAM device. The selected bit line is in communication with an MRAM cell to be read. A read current is applied through the MRAM cell to be read, and a reference current is applied through the selected bit line. A signal voltage is sensed on the selected bit line. The signal voltage is generated in response to the read current and the reference current. The signal voltage is coupled to an input of the sense amplifier, wherein the sense amplifier provides an offset corrected output reflective of the data state of the MRAM cell.
U.S. Pat. No. 6,845,037 (Han) teaches a reference cell that produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a thinly capacitively coupled thyristor (TCCT) based memory cell in an “on” state. The reference cell includes a negative differential resistance (NDR) device. A gate-like device is disposed adjacent to the NDR device and a first resistive element is coupled between the NDR device and the bit line. A second resistive element is coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of a TCCT based memory cell.
U.S. Pat. No. 6,711,068 (Subramanian, et al.) illustrates a memory with a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense amplifier. Each sub-array of the memory has an adjacent column decoder that couples data to a data line that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier that is impedance balanced with respect to the route taken by the data.
U.S. Patent Application 2004/0001360 (Subramanian et al.) provides an MRAM that has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
U.S. Pat. No. 6,754,123 (Perner, et al.) details a sensing circuit for determining the logic state of each memory cell in a resistive memory array. Each memory cell in the resistive memory array has current control isolation. The logic state of each memory cell can be determined relative to a reference cell having a pre-selected logic state. The sensing circuit includes a memory cell sensing circuit to determine a bias voltage of a memory cell. A reference cell sensing circuit determines a bias voltage of a reference cell. An isolation circuit applies an isolation voltage to turn off a current control element associated with each unselected memory cell. An adjusting circuit makes the bias voltage on the memory cell approximately equal to the bias voltage on the reference cell. A state determining circuit determines the logic state of the memory cell.
U.S. Pat. No. 6,791,887 (Hung, et al.) relates to a simplified reference current generator for a MRAM memory. The reference current generator is positioned in the vicinity of the memory cells of the MRAM, and applies reference elements which are the same as the magnetic tunnel junctions of the memory cell and bear the same cross voltages. The plurality of reference elements are used for forming the reference current generator by using one or several bit lines, and the voltage which is the same as the voltage of the memory cell is crossly connected to the reference elements so as to generate a plurality of current signals; and a peripheral IC circuit is used for generating the plurality of midpoint reference current signals and judging the data states. The midpoint reference current signals permit multiple-state memory cells, including the 2-states memory cell, and allow more accurate reading of the data.
U.S. Pat. No. 6,791,890 (Ooishi) describes a data read circuit that produces read data in accordance with a difference between currents flowing through first and second nodes, respectively. In a data read operation, a current transmitting circuit and a reference current generating circuit pass an access current corresponding to a passing current of a selected memory cell and a predetermined reference current through first and second nodes, respectively. In a test mode, a current switching circuit passes equal test currents through the first and second nodes instead of the access current and the reference current, respectively. Thereby, offset of the current sense amplifier in the data read circuit can be evaluated.